1. Field of the Invention
The present invention relates to a D/A converter (digital/analog converter) circuit (DAC), and in particular, to a DAC used for a driver circuit of an active matrix type semiconductor device. Further, the invention relates to an active matrix type semiconductor display device using the DAC.
2. Related Art
Recently, technologies for producing semiconductor devices having semiconductor thin films formed on inexpensive glass substrates, for example, thin film transistors (TFT) have been rapidly developed. The reason is an increased demand in active matrix type liquid crystal display devices.
The active matrix type liquid crystal display device is such that pixel TFTs are arrayed on pixel regions consisting of several ten thousands to several millions of pixels disposed like matrices, and electric charges taken in and taken out of pixel electrodes connected to the respective pixel TFTs are controlled by a switching feature of the pixel TFTs.
Further, active matrix type liquid crystal display devices of a digital drive system, which are capable of high rate drive, have been recognized in line with high minuteness and high image accuracy of the display devices.
A digital analog converter circuit (DAC) which converts digital video data, which are inputted from the peripheries, to analog signals (gradation voltages) is required for the active matrix type liquid crystal display devices of a digital drive system. There are various types of digital analog converter circuits. However, herein, an example of DAC, which is used for the active matrix type liquid crystal display devices, is illustrated.
Now, referring to FIG. 25, the drawing shows an example of a prior art DAC. The prior art DAC illustrated in FIG. 25 has xe2x80x9cnxe2x80x9d switches (SW0 through SWnxe2x88x921) which are controlled by respective bits of xe2x80x9cnxe2x80x9d bit digital data (D0 through Dnxe2x88x921), capacitances (C, 2C, . . . 2nxe2x88x921C) connected to the respective switches (SW0 through SWnxe2x88x921), and a reset switch (Res). Also, a power source VH and a power source VL are connected to the prior art DAC. Further, a capacitance CL is a load capacitance of a signal line connected to an output Vout. In addition, the ground power source is indicated by VG. However, the VG may be any optional constant power source.
The switches (SW0 through SWnxe2x88x921) are, respectively, connected to the power source VL when the bits corresponding to the inputted digital data (D0 through Dnxe2x88x921) are 0 (Lo), and to the power source VH when the corresponding bits are 1 (Hi).
A description is given of the prior art DAC sequentially. Actions of the prior art DAC are classified into a reset period (TR) and a data input period (TB) for description.
First, in the reset period TR, the reset switch Res is closed, all the bits (D0 through Dnxe2x88x921) of the digital data are 0 (Lo), and all the switches (SW0 through SWnxe2x88x921) are connected to the power source VL. FIG. 26(A) shows an equivalent circuit of the prior art DAC in this state.
After the termination of the reset period TR, since all the bits of the digital data (D0 through Dnxe2x88x921) are 0 (Lo), the initial value (default) QL of electric charge accumulated in the load capacitance CL shown in FIG. 26(A) becomes as in the following expression (19).
QLo=cLxc2x7(Vlxe2x88x92VG)xe2x80x83xe2x80x83(19)
After the reset period TR is terminated, a data writing period TE starts, and the digital data (D0 through Dnxe2x88x921) having optional bit information controls the switches (SW0 through SWnxe2x88x921). And, an electric charge is charged and discharged in compliance with the respective bit information, whereby a steady state arises thereafter. FIG. 26(B) shows the equivalent circuit at this time. The electric charges Q0, Q1, and QL accumulated in synthesized capacitances C0, C1, and CL become as in the following expressions (20a) through (20c).
Q0=c0xc2x7(VLxe2x88x92Vout)xe2x80x83xe2x80x83(20a)
Q1=c1xc2x7(VHxe2x88x92Vout)xe2x80x83xe2x80x83(20b)
QL=cLxc2x7(Voutxe2x88x92VG)xe2x80x83xe2x80x83(20c)
Herein, since the following expressions (21a) and (21b) are established,
c0=cxc2x7({overscore (D)}0+2{overscore (D)}1+4{overscore (D)}2+. . . +2nxe2x88x921{overscore (D)}nxe2x88x921)xe2x80x83xe2x80x83(21a)
c1=cxc2x7({overscore (D)}0+2{overscore (D)}1+4{overscore (D)}2+. . . +2nxe2x88x921{overscore (D)}nxe2x88x921)xe2x80x83xe2x80x83(21b)
the following expression (23) can be established by the preservation law of electric charge at the Vout.
QLo=QLxe2x88x92Q0xe2x88x92Q1xe2x80x83xe2x80x83(23)
the output VOUT becomes as in the following expression (24).                               V          out                =                              V            L                    +                                                    c                1                            ·              α              ·                              (                                                      V                    H                                    -                                      V                    L                                                  )                                                                    (                                                      2                    n                                    -                  1                                )                            ·              c                                                          (        24        )            
However, xcex1 is the ratio (in this specification, called a xe2x80x9cvoltage compression ratioxe2x80x9d) of the maximum voltage amplitude of the output VOUT to a voltage amplitude (VHxe2x88x92VL), wherein the xcex1 is expressed as follows;                     α        =                  1                      1            +                                          1                                                      2                    n                                    -                  1                                            ·                                                c                  L                                c                                                                        (        25        )            
As shown in FIG. 26(C), the output VOUT is in a linear relationship with respect to addresses (0 to 2nxe2x88x921). But since the output VOUT depends on a difference between VH and VL according to the expression (24), and changes in a linear form with respect to the addresses of digital data with the VL used as the reference potential, it is not possible to independently control the voltage amplitude and reference potential of the output VOUT.
Next, FIG. 27 shows another example of prior art DACs. The prior art DAC illustrated in FIG. 27 has xe2x80x9cnxe2x80x9d switches (SW0 through SWnxe2x88x921) which are controlled by respective bits of xe2x80x9cnxe2x80x9d bit digital data (D0 through Dnxe2x88x921), capacitances (C, 2C , . . . 2mxe2x88x921C, C, 2C, . . . 2nxe2x88x92mxe2x88x921C) connected to the respective switches (SW0 through SWnxe2x88x921), two reset switches (Res1 and Res2), and a coupling capacitance. Also, a power source VH and a power source VL are connected to the prior art DAC.
Also, FIG. 28 shows still another example of prior art DACs. The prior art DAC illustrated in FIG. 28 has xe2x80x9cnxe2x80x9d switches (SW0 through SWnxe2x88x921) which are controlled by respective bits of xe2x80x9cnxe2x80x9d bit digital data (D0 through Dnxe2x88x921), capacitances (C, 2C, . . . 2mxe2x88x921C, C, 2C . . . 2nxe2x88x92mxe2x88x921C) connected to the respective switches (SW0 through SWnxe2x88x921), and two reset switches (Res1 and Res2). Also, the prior art DAC shown in FIG. 28 is different from the prior art DAC shown in FIG. 27 in that a capacitance C is connected to the lower bit side circuit, and the coupling capacitance which connects a circuit corresponding to the lower bit to a circuit corresponding to the upper bit is different from that shown in FIG. 27.
In either the prior art DAC shown in FIG. 27 or the prior art DAC shown in FIG. 28, the switches (SW0 through SWnxe2x88x921) are, respectively, designed so as to be connected to the power source VL when inputted digital data (D0 through Dnxe2x88x921) are 0 (Lo), and to the power source VH when the inputted digital data are 1 (Hi).
The output VOUT of the prior art DAC shown in FIG. 27 becomes as in the following expression (26);                               V          out                =                              V            L                    +                                                    c                1                                                              (                                                            2                      n                                        -                    1                                    )                                ·                c                                      ·                          α              A                        ·                          (                                                V                  H                                -                                  V                  L                                            )                                                          (        26        )            
Further, the output VOUT of the prior art DAC shown in FIG. 28 becomes as in the following expression (27);                               V          out                =                              V            L                    +                                                    c                1                                                              2                  n                                ·                c                                      ·                          α              B                        ·                          (                                                V                  H                                -                                  V                  L                                            )                                                          (        27        )            
Herein, C1 is the same as that in the above expression (21b), and the following expressions are established, wherein xcex1A and xcex1B are voltage compression ratios.                               α          A                =                  1                      1            +                                                            2                  n                                                                      2                    n                                    -                  1                                            ·                                                c                  L                                c                                                                        (                  28a                )                                          α          B                =                  1                      1            +                                                            2                  m                                                  2                  n                                            ·                                                c                  L                                c                                                                        (                  28b                )            
Also, in these prior art DACs, it is understood that the output VOUT is in a linear relationship with respect to the addresses (0 through 2nxe2x88x921) of digital data as in the prior art DAC shown in FIG. 17(C). But, since, by the expressions (26) and (27), the output VOUT depends upon a difference between VH and VL, and changes in a linear form with respect to the addresses of digital data with the VL used as the reference voltage, it is not possible to independently control the voltage amplitude and reference potential of the output VOUT.
Therefore, the present invention was developed in view of the abovementioned problems and shortcomings. And, it is therefore an object of the invention to provide a DAC which is capable of independently controlling the voltage amplitude and reference potential of the output VOUT. Hereinafter, a description is given of a DAC according to the invention.
The present invention relates to a digital analog converter circuit which converts xe2x80x9cnxe2x80x9d bit digital data (wherein xe2x80x9cnxe2x80x9d is a natural number) to analog signals, wherein the respective bits of the xe2x80x9cnxe2x80x9d bit digital data control switches and further controls charge and discharge of electric charges in capacitances connected to the switches, and the digital analog converter circuit outputs analog signals with offset voltages used as a reference voltage.
The invention relates to a digital analog converter circuit which converts xe2x80x9cnxe2x80x9d bit digital data (wherein xe2x80x9cnxe2x80x9d is a natural number) to analog signals, wherein the digital analog converter circuit has xe2x80x9cnxe2x80x9d switches and xe2x80x9cnxe2x80x9d capacitances corresponding to the respective bits of the xe2x80x9cnxe2x80x9d bit digital data, the xe2x80x9cnxe2x80x9d switches corresponding to the xe2x80x9cnxe2x80x9d bits control charge and discharge of electric charges in the capacitances connected to each of the xe2x80x9cnxe2x80x9d switches, and the digital analog converter circuit outputs analog signals with offset voltages used as a reference voltage.
A digital analog converter circuit according to the invention, the digital analog converter circuit converts xe2x80x9cnxe2x80x9d bit digital data to analog signals, comprises switches controlled by the respective bits of the lower xe2x80x9cmxe2x80x9d bits (wherein xe2x80x9cnxe2x80x9d and xe2x80x9cmxe2x80x9d are natural numbers, and m less than n) of xe2x80x9cnxe2x80x9d bit digital data, and switches controlled by the respective bits of the upper (xe2x80x9cnxe2x80x9dxe2x88x92xe2x80x9cmxe2x80x9d) bits of the xe2x80x9cnxe2x80x9d bit digital data; capacitances connected to each of the switches controlled by the respective bits of the lower xe2x80x9cmxe2x80x9d bits, wherein each of the capacitances is of 2mxe2x88x921 times the unit capacitance; capacitances connected to each of the switches controlled by the respective bits of the upper xe2x80x9cnxe2x88x92mxe2x80x9d bits, wherein each of the capacitances is of 2nxe2x88x92mxe2x88x921 times the unit capacitance; a coupling capacitance; and two reset switches; wherein two power sources and an offset power source are connected to the digital analog converter circuit; the switches select either one of the two power sources, the two reset switches control charge of electric charges into the capacitances; and the digital analog converter circuit output analog signals, with the potential of the offset power source used as the reference potential, from a common connection end of the upper (xe2x80x9cnxe2x88x92mxe2x80x9d) bit capacitances of the xe2x80x9cnxe2x80x9d bit digital video data.
A digital analog converter circuit according to the invention comprises: a lower bit circuit portion controlled by the lower xe2x80x9cmxe2x80x9d bit (wherein xe2x80x9cnxe2x80x9d and xe2x80x9cmxe2x80x9d are natural numbers, xe2x80x9cmxe2x80x9d less than xe2x80x9cnxe2x80x9d)of data, wherein the lower bit circuit portion consists of switches controlled by the respective bits and capacitances connected to the switches, which has a capacitance being greater 2mxe2x88x921 times than the unit capacitance; an upper bit circuit portion controlled by the upper (xe2x80x9cnxe2x80x9dxe2x88x92xe2x80x9cmxe2x80x9d) bits of xe2x80x9cnxe2x80x9d bit digital data, wherein the upper bit circuit portion consists of switches controlled by the respective bits and capacitances connected to the switches, which has a capacitance being greater 2nxe2x88x92mxe2x88x921 times than the unit capacitance; a coupling capacitance consisting of the abovementioned unit capacitance for connecting the lower bit circuit portion to the upper bit circuit portion; and two reset switches; wherein two power sources and an offset power source are inputted therein; the two reset switches control charge of electric charges into the respective capacitances of the lower bit circuit portion and those of the upper bit circuit portion; the offset power source is inputted into the common connection end of the respective capacitances of the upper bit circuit portion; the respective switches of the lower bit circuit portion selects either one of the two power sources from information of the respective bits, and controls charge and discharge of electric charge of the capacitances connected to the respective switches; the respective switches of the upper bit circuit portion selects either one of the two power sources from information of the respective bits, and controls charge and discharge of electric charge of the capacitances connected to the respective switches; and analog signals in which the potential of the offset power source is used as a reference potential are outputted from the common connection end of the upper bit circuit portion.
In a DAC according to the invention, the output VOUT can determine its amplitude by a difference between VH and VL, and a change in a linear form with respect to the addresses of digital data while using the VL as the reference potential. That is, it is possible to independently control the voltage amplitude and reference potential of the output VOUT. Therefore, if the difference between VH and VL is constant, the same output VOUT can be obtained even though both VH and VL are made small. Accordingly, it is possible to suppress the power source voltage to a lower value, whereby a can be made small, that is, the capacitance C can be made small, and the layout region of the capacitance portion can be decreased.